1. Field of the Invention
The present invention relates principally to a semiconductor memory device and, in particular, a semiconductor memory device, such as an image memory device, for allowing data to be rewritten at high speed into memory cells.
2. Description of the Related Art
As an image memory device of this type, a dual port memory device has widely been employed which includes a random access memory (RAM) for allowing data access to be gained to any address and serial access memory (SAM) for allowing data to be accessed in a serial fashion. The general way of using the dual port memory is to enable an image display to be made by allowing data which are written into cells on a given row in RAM to be transferred to SAM and the data which are so transferred to be output from SAM in a serial fashion. It is necessary that, if all image data are to be cleared at once for a short period of time, all the data transferred from RAM to SAM be set to the same contents, that is, "1s" or "0s". In other words, it is necessary that all the data which are randomly stored as a varying combination of "1s" or "0s" on a given row of RAM be rewritten as the same data at one time.
In a memory array of a conventional RAM as shown in FIG. 3, a page mode is usually employed to allow cell data on a given row to be rewritten all as the same contents.
As appreciated from the timing chart of FIG. 4, with a row address strobe signal RAS at a low level, a given row in RAM is selected to enable, for example, a row line WL.sub.0. Then the column of RAM is sequentially selected by a column address strobe signal CAS. Upon enabling, for example, a column select signal CSL.sub.1 by an address ADR, the data which is output from an I/O buffer is written into memory cell MC.sub.1 via column line BL.sub.1. In the page mode, the columns are sequentially selected to allow data to be written column by column into all those cells associated with the row line WL.sub.0.
This method is effective because it directly uses the RAM function. However, it takes too long to rewrite RAM data as set forth above. That is, according to this method a time Cn .times. Tpc is required in rewriting data on a given row, where
Cn: the number of columns in a memory array and
Tpc: the page mode cycle time
A data rewriting system also may be employed to obtain those cell data on the row as all "0s" or all "1s" at one time instead of writing data column by column as in a page mode. This system may be used in an ordinary RAM, such as the memory array of the type shown in FIG. 3, in which case the operation timing is as shown in FIG. 5. That is, the system is of such a type that, subsequent to selecting a row in accordance with the row address with a row address strobe signal RAS set to a low level, each column is selected irrespective of the row address and then data "1s" or "0s" are caused to be written from an I/O buffer into all the cells which are connected to one row.
By the use of this system all the cell data on the row which are associated with an ordinary RAS cycle time can be set to the same level and data write operation can be achieved at high speed on that system. However, this system encounters a problem as set forth above.
Where use is made of a system capable of writing all associated data into those cells on a given row at one time, a write-in buffer of a greater capability is required to prevent an error upon the write-in of data. As a result, that buffer becomes very large in size. Furthermore, at the write time a fairly large current temporarily flows, causing a power source-induced noise. It is difficult to combat the aforementioned noise problem.